1. Field of the Invention
The present invention relates to a memory device comprising an array of memory cells, and to a method of performing access operations within such a memory device.
2. Description of the Prior Art
A typical memory device has an array of memory cells arranged as a plurality of rows and columns, word lines being coupled to the rows and bit lines being coupled to the columns. Access circuitry then performs read and write access operations in respect of selected memory cells using the word lines and bit lines. Control circuitry is used to control operation of the access circuitry when performing such access operations.
Since the memory cells (also referred to herein as memory bit cells) behave differently to the logic gates used to construct the access circuitry and control circuitry, it is known to employ a self-timed path (STP) delay circuit to seek to provide an indication of an access timing delay associated with accessing the memory cells, with the access circuitry then being controlled having regard to that indication produced by the STP delay circuitry.
Modern memory devices as used in System-on-Chips (SoCs) are often designed to use dual voltage domains, with the memory array being operated in an array voltage domain (also referred to as a core voltage domain) whilst much of the associated access circuitry and the control circuitry then operates in a peripheral voltage domain. The use of such a dual voltage domain enables the memory array to retain data by continuing to be powered while the peripheral circuits are shut down, thus assisting in reducing power consumption when the memory device is not being used. The STP delay circuitry would typically be operated in the peripheral voltage domain, in order to maximise the power consumption benefits achievable when the memory device is not being used.
Traditionally, the peripheral voltage supply used in the peripheral voltage domain has been arranged to be less than the core voltage supply used in the core voltage domain. Typically, memory designs have been able to cope with situations where the peripheral voltage supply is less than or equal to the core voltage supply by delaying a delay path within the STP delay circuitry using extra margin adjustment (EMA) pins. However, due to Power Management IC (PMIC) variation on the chip in modern memory designs, it is no longer possible to guarantee that the core voltage supply will be higher than the peripheral voltage supply.
In such situations, it has been found that the STP delay circuitry operating in the peripheral voltage domain may produce a delay indication which is insufficient to account for worst case access timing delay within the array of memory cells, thus giving rise to potential errors in the read and write operations performed in respect of the memory device. It would hence be desirable to provide a more reliable STP delay mechanism that can accommodate situations where the peripheral voltage supply is higher than the core voltage supply.